Whole System Timing

Sometimes when developing on DSPs we need to keep precise timing records between inputs and outputs. For example, the time between an incoming sinusoid, work performed on it, and output sinusoid might be expected to be 5ms in a requirement. But care should be taken to be clear on what the requirements mean by time between "input" and "output". It could be referring to the actual DSP or it could be referring to the entire system. Each component has a delay attributed to it. For example just because the signal is output from the DSP doesn't mean it won't go through filters, upconverters, digital to analog converters, splitters, amplifiers, etc. These could be in the form of FPGAs from Xilinx, other DSPs, or separate "black boxes". You need to ensure that the timing development reflects the entire system. Otherwise the system may be completely non-functional.